1. Field of the Invention
The present invention relates to semiconductor packaging technology, and more particularly to a stack package using a flexible double wiring substrate.
2. Description of the Related Art
It has been long desired to provide low-cost semiconductor chip packages that are lighter, smaller, faster and multi-functional, having improved reliability. In order to satisfy this goal, a package assembly technique has been developed, utilizing a recently introduced Ball Grid Array (BGA) package. Compared to the conventional plastic package, the BGA package reduces the mounting area on a motherboard and has improved electrical properties.
The BGA package uses a printed circuit board instead of a conventional plastic package lead frame. The surface of the printed circuit board that is opposite to the surface with a semiconductor chip attached thereto, contains an area for forming solder balls. Thus, the BGA package improves the mounting density on the motherboard but is limited by the size of the printed circuit board. That is, since the printed circuit board requires a predetermined area free of circuit wiring for mounting the semiconductor chip, the printed circuit board has a greater size than that of the semiconductor chip. Under these circumstances, a Chip Scale Package (CSP) has been introduced.
Several manufacturers in the U.S., JAPAN and Korea have recently developed various types of the CSP. One leading type of the CSPs is a BGA package using a tape circuit board comprising a flexible polyimide tape with circuit patterns formed on the polyimide tape. Usually, electrical connections attaching the semiconductor chip and the tape circuit board employ a beam lead bonding method or a wire bonding method.
FIG. 1 is a cross-sectional view of a CSP 100 using a wire bonding method. With reference to FIG. 1, the CSP 100 comprises a tape circuit board 20 with a window 22 at the center, and a semiconductor chip 10 that is attached to a bottom surface of tape circuit board 20. Semiconductor chip 10 is electrically connected to tape circuit board 20 by bonding electrode pads 12 to wiring pattern 23 with bonding wires 40 through window 22. Bonding wires 40 and the outer surface of semiconductor chip 10 exposed through window 22 and around the peripheral surface are encapsulated by a liquid encapsulant to form resin molding portions 50 and 53. Connection terminals 60 such as solder balls are formed on portions of wiring patterns 23 exposed from connection holes 28 on the upper surface of tape circuit board 20.
Tape circuit board 20 comprises a polyimide tape 21 with window 22 and wiring patterns 23 formed on the upper surface of polyimide tape 21. Wiring patterns 23 are around window 22 and include substrate pads 24, which are connected to corresponding electrode pads 12, and connection pads 26, to which the connection terminals 60 are attached. The upper surface of polyimide tape 21 not covered by connection pads 26 is coated with a protection layer 25 made, for example, of Photo Solder Resist (PSR). An elastomer 27 is formed on the lower surface of polyimide tape 21.
In addition to the CSP, other techniques are developed so as to reduce the size of the package, for example, a stack packaging technique for three-dimensionally stacking a plurality of semiconductor chips or a plurality of packages. A package implemented by this technique is usually referred to as a stack package.
Since a stack package using the conventional semiconductor packages employs packages that have already passed reliability tests, the stack package has a low failure rate but is comparatively thick. On the other hand, a stack package stacking semiconductor chips, (referred to as a “stack chip package”), is much thinner. The stack chip package, however, employs chips that were not previously inspected in reliability tests, thereby increasing failure rates.
Therefore, if a stack package is manufactured by stacking the above-described CSPs, it would be desirable for stack package to have both advantages: thinness and reliability. However, it is not easy to stack the CSPs, each of which is mounted on the printed circuit board. That is, since the conventional CSP contains only solder bumps formed on the upper surface of the tape circuit board for external connection terminals, it is difficult to three-dimensionally stack the conventional CSPs.